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Making a URISC Processor: Micro-Instruction Encoding

 In the last post I described the micro-instructions that are to be executed to execute the SUBNEG instruction. Given below is the table I had posted previously:



I realized later that it still might not be entirely clear as to how this was working so I have made a GIF of the same to better explain how the "Subtraction" instruction is executed.
Pretty cool huh?.... no??? okay 😢

In The GIF it is assumed that the following data is stored in the RAM:

Address   Byte

#0000       #32 [B(l)]

#0001       #00 [B(h)]

#0002       #33 [A(l)]

#0003       #00 [A(h)]

#0004       #20 [C(l)]

#0005       #01 [C(h)]

#0032       #07 [Data]

#0033       #09 [Data]


The next thing we need to do is try to optimize this process.
In the above GIF you may or may not have noticed that Incrementing the Program Counter is actually an independent process and other elements such as the Mem. Add Ptr. and RAM are idle.
So, we can actually do the Increment operation while the rest of the processor does something else i.e. run operations in parallel.
With this idea in mind I rewrote the micro instructions:
The above micro-instructions take 2 steps less than the previous micro-instructions. Now, if the result is a negative number then the instruction takes 13 steps and if the number is not negative it takes 10 steps.

This sequencing is of steps is done by a "binary counter". Binary counters count to powers of 2, i.e. a 2 bit counter has 4 steps (0 to 3), 3 bit counter has 8 steps (0 to 7) and so on.
Hence, to run a 13 step sequence we need a 4 bit counter i.e. it counts from 0 to 15 and then loops back to zero. 
Since, our sequence is 13 steps or 10 steps long (depending if the result is negative or not) we need a way to abruptly cause the counter to loop back to zero before it reaches 15.
To do so we can use the counter's reset line. So, if we want the counter to only count till 10 we reset it as soon as it counts 11. Similarly, for a 13 step sequence we reset it at 14.

Now, let me talk about encoding these instructions. The encoding process is pretty straightforward. For executing any step we need to activate the control lines of the various elements of our processor.

For example, PC on address bus: RAM to MAP(L) can be done by activating the control lines- PC OE, RAM OE and MAP(L) IE.
By the same logic a complete table can be made with binary notation where 1 represents the activation of a control line and 0 represents the deactivation of the line.

Shown above is the table I made for the various control lines. The step goes from 0 to 15. The 'X' represents 'don't cares' i.e. since the counter is reset before hand and will never reach this step these values are not relevant to us. Alongside the step column there is an MSB column that basically dictates which sequence is run if the result is not negative and which sequence is run if the sequence is negative.

Finally, we need to convert the step numbers, written in decimal number system, to binary. Doing so, we get this table:

This is the final "Truth Table" for the control unit of my URISC processor with a 5-bit input (MSB and Step) and a 12-bit output (control word).

In the upcoming posts I will try and explain the actual hardware implementation of the processor... till then....

Got any queries???E-Mail me at: shashwath.sundar@gmail.com

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