Simple But Nerdy

 In the last post I described the micro-instructions that are to be executed to execute the SUBNEG instruction. Given below is the table I had posted previously: I realized later that it still might not be entirely clear as to how this was working so I have made a GIF of the same to better explain how the "Subtraction" instruction is executed. Pretty cool huh?.... no??? okay 😢 In The GIF it is assumed that the following data is stored in the RAM: Address    Byte #0000           #32  [B(l)] #0001         #00  [B(h)] #0002         #33  [A(l)] #0003       #00  [A(h)] #0004       #20  [C(l)] #0005       #01  [C(h)] #0032         #07 [Data] #0033       #09 [Data] The next thing we need to do is try to optimize this process. In the above GIF you may or may...

In the previous posts I have explained what the instruction does, the architecture and the control word for controlling all the elements of the architecture. Now, let me try and explain how the instruction is actually entered in RAM. The 'SUBNEG' instruction as I had explained in the first post has three 16-Bit operands. The RAM stores only one 'Byte' or 8-Bits in each address/memory location. So, we need to split each 16-Bit number further into 2 parts (2 bytes) and save them in consecutive addresses. After splitting the number into 2 bytes we can name them as 'Higher Byte' and  'Lower Byte'. So, suppose the number was A where, A= 1011 0100 1100 1101 ( #B4CD in hexadecimal) I will call the lower byte as A(l) and higher byte as A(h) hence, A(h)= 1011 0100 ( #B4 ) A(l)= 1100 1101 ( #CD ) now that we have split the numbers we need to store them in 2 consecutive addresses lets assume for now the addresses are address #0000 and address #0001 . So, now t...

 In the previous post I had discussed the basic idea of the URISC processor and the 'SUBNEG' instruction. In this post I will try and explain how the various registers are controlled. First let me talk about the control word. A control word is a a large binary number (also called a word) that is used to control the various elements in the processor. The arrows in the block diagram show the direction in which the data can move and this can actually give us some insight to the control word. For eg, the program counter has bidirectional arrow i.e. it can read as well as write to the 16-bit address bus. So, the program counter needs a read and write control line. Going by the same idea all the control lines can be figured out. The table below, shows all the various control lines of each component. In the table 'IE' is Input Enable (read line) and 'OE' is Output Enable (Write line). The 'inc' control line is for incrementing the program counter by 1. 'RST...

So a while back I saw this video on Youtube by "Gary Explains" talking about a "One Instruction Set Computer". For those who do not know, a computer processor does a fixed set of things or follows a fixed set of instructions. Usually modern processors have hundreds of instructions. In the OISC or URISC (Ultimate Reduced Instruction Set Computer) processor the idea is to have one universal instruction that the processor executes that allows the programmer to write any program. The first time I heard of this idea I fell off my chair with excitement (Literally). My mind was really blown by the fact that you could write any program with just one instruction. So after going through what "Gary" on Youtube had to offer... I sat down and tried to come up with a design of this hypothetical processor that executes only one instruction. In the video Gary talked about a processor that executed an instruction called 'SUBLEQ' which simply means, SUB tract and th...